fpga
FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.
51
44%
Does it follow best practices?
Impact
Pending
No eval scenarios have been run
Passed
No known issues
Optimize this skill with Tessl
npx tessl skill review --optimize ./fpga/SKILL.mdQuality
Discovery
54%Based on the skill's description, can an agent find and select it at the right time? Clear, specific descriptions lead to better discovery.
The description has strong trigger terms for the FPGA/hardware development domain and is distinctive enough to avoid conflicts with other skills. However, it fails to specify concrete actions (what the skill actually does beyond 'guidelines') and completely lacks explicit trigger guidance for when Claude should select this skill.
Suggestions
Add a 'Use when...' clause specifying triggers like 'Use when the user asks about FPGA design, Vivado projects, RTL coding, timing constraints, or AXI bus implementation'
Replace 'guidelines covering' with specific actions like 'Provides coding standards for SystemVerilog, debugging strategies for timing closure, and implementation patterns for AXI interfaces'
Clarify what concrete help this skill provides - does it review code, generate templates, explain concepts, or troubleshoot issues?
| Dimension | Reasoning | Score |
|---|---|---|
Specificity | Names the domain (FPGA development) and lists several specific areas (Vivado, SystemVerilog, timing closure, AXI interfaces, hardware optimization), but uses 'guidelines covering' which is vague about what concrete actions the skill performs. | 2 / 3 |
Completeness | Describes what domain it covers but lacks any explicit 'Use when...' clause or trigger guidance. The 'when' is entirely missing, which per rubric guidelines caps this at maximum 2, and since the 'what' is also weak (just 'guidelines covering'), this scores 1. | 1 / 3 |
Trigger Term Quality | Includes strong natural keywords users would say: 'FPGA', 'Vivado', 'SystemVerilog', 'timing closure', 'AXI interfaces', 'hardware optimization' - these are all terms engineers naturally use when seeking help in this domain. | 3 / 3 |
Distinctiveness Conflict Risk | FPGA development with specific tools (Vivado) and protocols (AXI) creates a clear niche that is unlikely to conflict with other skills - this is a specialized hardware domain with distinct terminology. | 3 / 3 |
Total | 9 / 12 Passed |
Implementation
35%Reviews the quality of instructions and guidance provided to agents. Good implementation is clear, handles edge cases, and produces reliable results.
This skill provides a broad overview of FPGA development topics but lacks the concrete, executable guidance that would make it actionable. The content reads more like a checklist of considerations than a practical guide with specific commands, code examples, or Vivado-specific workflows. The absence of any SystemVerilog code snippets, XDC constraint examples, or Tcl commands significantly limits its utility.
Suggestions
Add concrete SystemVerilog code examples for key patterns (e.g., CDC synchronizer, AXI handshake, clock gating template)
Include specific XDC constraint syntax examples for timing constraints and multi-cycle paths
Provide a step-by-step Vivado workflow with explicit validation checkpoints (e.g., 'Run timing analysis after synthesis: report_timing_summary -delay_type min_max')
Add Tcl command examples for common Vivado operations like ILA insertion and timing report generation
| Dimension | Reasoning | Score |
|---|---|---|
Conciseness | Content is reasonably efficient but includes some general guidance that Claude would already know (e.g., 'maintain consistent naming conventions', 'write detailed testbenches'). Could be tightened by removing obvious best practices. | 2 / 3 |
Actionability | Almost entirely abstract guidance with no concrete code examples, specific commands, or executable snippets. Statements like 'use proper CDC techniques' and 'optimize LUTs' describe rather than instruct with actionable specifics. | 1 / 3 |
Workflow Clarity | Some implicit sequencing exists (e.g., timing closure section suggests a workflow), but no explicit step-by-step processes with validation checkpoints. Missing concrete validation steps for synthesis/implementation flows. | 2 / 3 |
Progressive Disclosure | Content is organized into logical sections with clear headers, but everything is inline with no references to detailed documentation. Advanced techniques section could benefit from linking to separate detailed guides. | 2 / 3 |
Total | 7 / 12 Passed |
Validation
62%Checks the skill against the spec for correct structure and formatting. All validation checks must pass before discovery and implementation can be scored.
Validation — 10 / 16 Passed
Validation for skill structure
| Criteria | Description | Result |
|---|---|---|
description_trigger_hint | Description may be missing an explicit 'when to use' trigger hint (e.g., 'Use when...') | Warning |
metadata_version | 'metadata' field is not a dictionary | Warning |
license_field | 'license' field is missing | Warning |
body_examples | No examples detected (no code fences and no 'Example' wording) | Warning |
body_output_format | No obvious output/return/format terms detected; consider specifying expected outputs | Warning |
body_steps | No step-by-step structure detected (no ordered list); consider adding a simple workflow | Warning |
Total | 10 / 16 Passed | |
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- mindrally/skills
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