fpga

FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.

Quality

27%

Does it follow best practices?

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tessl review fix ./fpga/SKILL.md

Quality

Content

22%

Reviews the quality of instructions and guidance provided to agents. Good implementation is clear, handles edge cases, and produces reliable results.

This skill reads as a high-level FPGA best-practices checklist rather than actionable guidance for Claude. It lacks concrete code examples (SystemVerilog modules, XDC constraints, Vivado TCL commands), specific workflows with validation steps, and any novel information beyond what Claude would already know about FPGA development. The content would need significant rework to be useful as a skill.

Suggestions

Add concrete, executable examples: SystemVerilog code for CDC synchronizers, AXI interface templates, XDC constraint syntax, and Vivado TCL commands for common operations.

Define clear multi-step workflows with validation checkpoints, e.g., a timing closure workflow: run synthesis → check timing report → identify violations → add pipeline stages → re-run → verify closure.

Remove generic advice Claude already knows (e.g., 'maintain consistent naming conventions', 'write detailed testbenches') and replace with project-specific patterns, anti-patterns, or tool-specific gotchas.

Add concrete examples of common pitfalls with before/after code, such as incorrect CDC patterns vs. correct ones, or synthesis-unfriendly vs. synthesis-friendly SystemVerilog constructs.

Dimension	Reasoning	Score
Conciseness	The content is moderately efficient but includes many generic best-practice statements that Claude already knows (e.g., 'Structure designs into small, reusable modules to enhance readability and testability', 'Write detailed, self-checking testbenches'). These are textbook-level guidelines that don't add novel, actionable knowledge.	2 / 3
Actionability	The skill is almost entirely abstract guidance with no concrete code examples, specific commands, XDC constraint syntax, SystemVerilog snippets, or Vivado TCL commands. Statements like 'Use synchronizers or FIFOs to handle CDC safely' and 'Optimize LUTs, flip-flops, and block RAM through efficient SystemVerilog' describe rather than instruct.	1 / 3
Workflow Clarity	There are no sequenced workflows, no validation checkpoints, and no feedback loops. The timing closure section lists steps but without clear ordering, specific tool commands, or verification gates. FPGA development involves multi-step processes (synthesis → implementation → timing analysis → bitstream) that are not articulated as workflows.	1 / 3
Progressive Disclosure	The content is organized into logical sections with headers and sub-headers, which provides some structure. However, there are no references to external files, no bundle files, and some sections (like Advanced Techniques) could benefit from being split out. The organization is reasonable for a standalone file but doesn't leverage progressive disclosure.	2 / 3
	Total	6 / 12 Passed

Description

32%

Based on the skill's description, can an agent find and select it at the right time? Clear, specific descriptions lead to better discovery.

The description identifies a clear technical domain (FPGA development) and lists relevant subtopics, but it reads more like a topic list than an actionable skill description. It lacks concrete actions (what the skill actually does) and completely omits trigger guidance (when Claude should use it), significantly reducing its effectiveness for skill selection.

Suggestions

Add an explicit 'Use when...' clause, e.g., 'Use when the user asks about FPGA design, Vivado projects, SystemVerilog coding, timing constraints, or AXI bus integration.'

Replace 'guidelines covering' with specific actions, e.g., 'Provides coding standards for SystemVerilog, debugs timing closure issues, configures AXI interfaces, and optimizes FPGA resource utilization.'

Include additional natural trigger terms users might say, such as 'Xilinx', 'RTL', 'synthesis', 'bitstream', 'constraints', 'HDL', or 'Verilog'.

Dimension	Reasoning	Score
Specificity	Names the domain (FPGA development) and lists several specific topics (Vivado, SystemVerilog, timing closure, AXI interfaces, hardware optimization), but uses the vague word 'guidelines' and 'covering' rather than describing concrete actions like 'write', 'debug', 'optimize', or 'configure'.	2 / 3
Completeness	Describes what the skill covers at a high level but completely lacks any 'Use when...' clause or explicit trigger guidance for when Claude should select this skill. Per the rubric, a missing 'Use when...' clause caps completeness at 2, and the 'what' is also weak (just 'guidelines covering'), warranting a score of 1.	1 / 3
Trigger Term Quality	Includes good technical keywords like 'Vivado', 'SystemVerilog', 'timing closure', 'AXI interfaces', and 'FPGA' that users would naturally mention, but misses common variations like 'HDL', 'Verilog', 'RTL', 'synthesis', 'bitstream', 'constraints', or 'Xilinx'.	2 / 3
Distinctiveness Conflict Risk	The FPGA/Vivado/SystemVerilog domain is fairly niche and unlikely to conflict with most other skills, but the word 'guidelines' is generic and could overlap with other hardware or coding style guide skills. More specific action-oriented language would improve distinctiveness.	2 / 3
	Total	7 / 12 Passed

Validation

100%

Warnings & errors only

Checks the skill against the spec for correct structure and formatting. All validation checks must pass before discovery and implementation can be scored.

Validation — 11 / 11 Passed

Validation for skill structure

No warnings or errors.

Repository: mindrally/skills
Path: fpga/SKILL.md
Commit: 05a7130

Reviewed: about 15 hours ago

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