Package cpu implements processor feature detection for various CPU architectures.
golang.org/x/sys/cpuThe cpu package provides runtime detection of CPU features across different architectures including x86/AMD64, ARM, ARM64, PowerPC, RISC-V, s390x, MIPS, and LoongArch. It allows Go programs to query hardware capabilities and make architecture-specific optimizations.
import "golang.org/x/sys/cpu"const IsBigEndian = falseIsBigEndian records whether the GOARCH's byte order is big endian.
var Initialized boolInitialized reports whether the CPU features were initialized. For some GOOS/GOARCH combinations initialization of the CPU features depends on reading an operating specific file, e.g. /proc/self/auxv on linux/arm. Initialized will report false if reading the file fails.
var ARM struct {
_ CacheLinePad
HasSWP bool // SWP instruction support
HasHALF bool // Half-word load and store support
HasTHUMB bool // ARM Thumb instruction set
Has26BIT bool // Address space limited to 26-bits
HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support
HasFPA bool // Floating point arithmetic support
HasVFP bool // Vector floating point support
HasEDSP bool // DSP Extensions support
HasJAVA bool // Java instruction set
HasIWMMXT bool // Intel Wireless MMX technology support
HasCRUNCH bool // MaverickCrunch context switching and handling
HasTHUMBEE bool // Thumb EE instruction set
HasNEON bool // NEON instruction set
HasVFPv3 bool // Vector floating point version 3 support
HasVFPv3D16 bool // Vector floating point version 3 D8-D15
HasTLS bool // Thread local storage support
HasVFPv4 bool // Vector floating point version 4 support
HasIDIVA bool // Integer divide instruction support in ARM mode
HasIDIVT bool // Integer divide instruction support in Thumb mode
HasVFPD32 bool // Vector floating point version 3 D15-D31
HasLPAE bool // Large Physical Address Extensions
HasEVTSTRM bool // Event stream support
HasAES bool // AES hardware implementation
HasPMULL bool // Polynomial multiplication instruction set
HasSHA1 bool // SHA1 hardware implementation
HasSHA2 bool // SHA2 hardware implementation
HasCRC32 bool // CRC32 hardware implementation
_ CacheLinePad
}ARM contains the supported CPU features of the current ARM (32-bit) platform. All feature flags are false if:
var ARM64 struct {
_ CacheLinePad
HasFP bool // Floating-point instruction set (always available)
HasASIMD bool // Advanced SIMD (always available)
HasEVTSTRM bool // Event stream support
HasAES bool // AES hardware implementation
HasPMULL bool // Polynomial multiplication instruction set
HasSHA1 bool // SHA1 hardware implementation
HasSHA2 bool // SHA2 hardware implementation
HasCRC32 bool // CRC32 hardware implementation
HasATOMICS bool // Atomic memory operation instruction set
HasHPDS bool // Hierarchical permission disables in translations tables
HasLOR bool // Limited ordering regions
HasPAN bool // Privileged access never
HasFPHP bool // Half precision floating-point instruction set
HasASIMDHP bool // Advanced SIMD half precision instruction set
HasCPUID bool // CPUID identification scheme registers
HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
HasJSCVT bool // Javascript conversion from floating-point to integer
HasFCMA bool // Floating-point multiplication and addition of complex numbers
HasLRCPC bool // Release Consistent processor consistent support
HasDCPOP bool // Persistent memory support
HasSHA3 bool // SHA3 hardware implementation
HasSM3 bool // SM3 hardware implementation
HasSM4 bool // SM4 hardware implementation
HasASIMDDP bool // Advanced SIMD double precision instruction set
HasSHA512 bool // SHA512 hardware implementation
HasSVE bool // Scalable Vector Extensions
HasSVE2 bool // Scalable Vector Extensions 2
HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
HasDIT bool // Data Independent Timing support
HasI8MM bool // Advanced SIMD Int8 matrix multiplication instructions
_ CacheLinePad
}ARM64 contains the supported CPU features of the current ARMv8(aarch64) platform. If the current platform is not arm64 then all feature flags are false.
var Loong64 struct {
_ CacheLinePad
HasLSX bool // support 128-bit vector extension
HasLASX bool // support 256-bit vector extension
HasCRC32 bool // support CRC instruction
HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction
HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D} instruction
_ CacheLinePad
}The booleans in Loong64 contain the correspondingly named cpu feature bit. The struct is padded to avoid false sharing.
var MIPS64X struct {
_ CacheLinePad
HasMSA bool // MIPS SIMD architecture
_ CacheLinePad
}MIPS64X contains the supported CPU features of the current mips64/mips64le platforms. If the current platform is not mips64/mips64le or the current operating system is not Linux then all feature flags are false.
var PPC64 struct {
_ CacheLinePad
HasDARN bool // Hardware random number generator (requires kernel enablement)
HasSCV bool // Syscall vectored (requires kernel enablement)
IsPOWER8 bool // ISA v2.07 (POWER8)
IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
_ CacheLinePad
}PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms. If the current platform is not ppc64/ppc64le then all feature flags are false.
For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00, since there are no optional categories. There are some exceptions that also require kernel support to work (DARN, SCV), so there are feature bits for those as well. The struct is padded to avoid false sharing.
var RISCV64 struct {
_ CacheLinePad
HasFastMisaligned bool // Fast misaligned accesses
HasC bool // Compressed instruction-set extension
HasV bool // Vector extension compatible with RVV 1.0
HasZba bool // Address generation instructions extension
HasZbb bool // Basic bit-manipulation extension
HasZbs bool // Single-bit instructions extension
HasZvbb bool // Vector Basic Bit-manipulation
HasZvbc bool // Vector Carryless Multiplication
HasZvkb bool // Vector Cryptography Bit-manipulation
HasZvkt bool // Vector Data-Independent Execution Latency
HasZvkg bool // Vector GCM/GMAC
HasZvkn bool // NIST Algorithm Suite (AES/SHA256/SHA512)
HasZvknc bool // NIST Algorithm Suite with carryless multiply
HasZvkng bool // NIST Algorithm Suite with GCM
HasZvks bool // ShangMi Algorithm Suite
HasZvksc bool // ShangMi Algorithm Suite with carryless multiplication
HasZvksg bool // ShangMi Algorithm Suite with GCM
_ CacheLinePad
}RISCV64 contains the supported CPU features and performance characteristics for riscv64 platforms. The booleans in RISCV64, with the exception of HasFastMisaligned, indicate the presence of RISC-V extensions.
It is safe to assume that all the RV64G extensions are supported and so they are omitted from this structure. As riscv64 Go programs require at least RV64G, the code that populates this structure cannot run successfully if some of the RV64G extensions are missing. The struct is padded to avoid false sharing.
var S390X struct {
_ CacheLinePad
HasZARCH bool // z/Architecture mode is active [mandatory]
HasSTFLE bool // store facility list extended
HasLDISP bool // long (20-bit) displacements
HasEIMM bool // 32-bit immediates
HasDFP bool // decimal floating point
HasETF3EH bool // ETF-3 enhanced
HasMSA bool // message security assist (CPACF)
HasAES bool // KM-AES{128,192,256} functions
HasAESCBC bool // KMC-AES{128,192,256} functions
HasAESCTR bool // KMCTR-AES{128,192,256} functions
HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
HasGHASH bool // KIMD-GHASH function
HasSHA1 bool // K{I,L}MD-SHA-1 functions
HasSHA256 bool // K{I,L}MD-SHA-256 functions
HasSHA512 bool // K{I,L}MD-SHA-512 functions
HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
HasVX bool // vector facility
HasVXE bool // vector-enhancements facility 1
_ CacheLinePad
}S390X contains the supported CPU features of the current IBM Z (s390x) platform. If the current platform is not IBM Z then all feature flags are false.
S390X is padded to avoid false sharing. Further HasVX is only set if the OS supports vector registers in addition to the STFLE feature bit being set.
var X86 struct {
_ CacheLinePad
HasAES bool // AES hardware implementation (AES NI)
HasADX bool // Multi-precision add-carry instruction extensions
HasAVX bool // Advanced vector extension
HasAVX2 bool // Advanced vector extension 2
HasAVX512 bool // Advanced vector extension 512
HasAVX512F bool // Advanced vector extension 512 Foundation Instructions
HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions
HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions
HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions
HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions
HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions
HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions
HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add
HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions
HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision
HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision
HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions
HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations
HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions
HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions
HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions
HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2
HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms
HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions
HasAMXTile bool // Advanced Matrix Extension Tile instructions
HasAMXInt8 bool // Advanced Matrix Extension Int8 instructions
HasAMXBF16 bool // Advanced Matrix Extension BFloat16 instructions
HasBMI1 bool // Bit manipulation instruction set 1
HasBMI2 bool // Bit manipulation instruction set 2
HasCX16 bool // Compare and exchange 16 Bytes
HasERMS bool // Enhanced REP for MOVSB and STOSB
HasFMA bool // Fused-multiply-add instructions
HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
HasPOPCNT bool // Hamming weight instruction POPCNT.
HasRDRAND bool // RDRAND instruction (on-chip random number generator)
HasRDSEED bool // RDSEED instruction (on-chip random number generator)
HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
HasSSE3 bool // Streaming SIMD extension 3
HasSSSE3 bool // Supplemental streaming SIMD extension 3
HasSSE41 bool // Streaming SIMD extension 4 and 4.1
HasSSE42 bool // Streaming SIMD extension 4 and 4.2
HasAVXIFMA bool // Advanced vector extension Integer Fused Multiply Add
HasAVXVNNI bool // Advanced vector extension Vector Neural Network Instructions
HasAVXVNNIInt8 bool // Advanced vector extension Vector Neural Network Int8 instructions
_ CacheLinePad
}X86 contains the supported CPU features of the current X86/AMD64 platform. If the current platform is not X86/AMD64 then all feature flags are false.
X86 is padded to avoid false sharing. Further the HasAVX and HasAVX2 are only set if the OS supports XMM and YMM registers in addition to the CPUID feature bit being set.
type CacheLinePad struct {
// Has unexported fields.
}CacheLinePad is used to pad structs to avoid false sharing. This type is used as padding in the architecture-specific feature structs to ensure each struct occupies its own cache line, preventing false sharing between CPU cores.
Check for specific CPU features before using specialized instructions:
package main
import (
"fmt"
"golang.org/x/sys/cpu"
)
func main() {
// Check if CPU features were successfully initialized
if !cpu.Initialized {
fmt.Println("Warning: CPU feature detection failed")
}
// Check x86/AMD64 features
if cpu.X86.HasAVX2 {
fmt.Println("AVX2 is available")
// Use AVX2-optimized code path
}
if cpu.X86.HasAES {
fmt.Println("Hardware AES is available")
// Use hardware-accelerated AES
}
// Check ARM64 features
if cpu.ARM64.HasNEON {
fmt.Println("NEON SIMD is available")
// Use NEON-optimized code
}
// Check for cryptographic acceleration
if cpu.ARM64.HasAES && cpu.ARM64.HasSHA2 {
fmt.Println("ARM crypto extensions available")
}
}Select optimal code paths based on available features:
package main
import (
"golang.org/x/sys/cpu"
)
func processData(data []byte) []byte {
// Select implementation based on CPU features
switch {
case cpu.X86.HasAVX512:
return processDataAVX512(data)
case cpu.X86.HasAVX2:
return processDataAVX2(data)
case cpu.ARM64.HasNEON:
return processDataNEON(data)
default:
return processDataGeneric(data)
}
}
func processDataAVX512(data []byte) []byte {
// AVX-512 optimized implementation
return data
}
func processDataAVX2(data []byte) []byte {
// AVX2 optimized implementation
return data
}
func processDataNEON(data []byte) []byte {
// NEON optimized implementation
return data
}
func processDataGeneric(data []byte) []byte {
// Portable fallback implementation
return data
}Verify that all required features are available:
package main
import (
"fmt"
"golang.org/x/sys/cpu"
)
func canUseOptimizedCrypto() bool {
// Check if we can use hardware-accelerated crypto
if cpu.X86.HasAES && cpu.X86.HasPCLMULQDQ {
return true
}
if cpu.ARM64.HasAES && cpu.ARM64.HasPMULL {
return true
}
return false
}
func main() {
if canUseOptimizedCrypto() {
fmt.Println("Using hardware-accelerated cryptography")
} else {
fmt.Println("Using software cryptography")
}
}package main
import (
"fmt"
"golang.org/x/sys/cpu"
)
func main() {
if cpu.PPC64.IsPOWER9 {
fmt.Println("Running on POWER9 or newer (implies POWER8)")
// Use POWER9-specific instructions
} else if cpu.PPC64.IsPOWER8 {
fmt.Println("Running on POWER8")
// Use POWER8-specific instructions
}
if cpu.PPC64.HasDARN {
fmt.Println("Hardware RNG available (kernel support required)")
}
}package main
import (
"fmt"
"golang.org/x/sys/cpu"
)
func main() {
if cpu.RISCV64.HasV {
fmt.Println("RISC-V Vector extension (RVV 1.0) available")
}
if cpu.RISCV64.HasZbb {
fmt.Println("Basic bit-manipulation extension available")
}
if cpu.RISCV64.HasZvkn {
fmt.Println("Vector crypto (NIST algorithms) available")
}
if cpu.RISCV64.HasFastMisaligned {
fmt.Println("Fast misaligned memory access supported")
}
}Always check cpu.Initialized - On some platforms, feature detection may fail. Check this variable before relying on feature flags.
Use feature flags, not architecture detection - Check for specific features (like cpu.X86.HasAVX2) rather than detecting the architecture, as this provides finer-grained control.
Provide fallbacks - Always have a portable implementation that works when specialized features are not available.
Be aware of OS requirements - Some features (like AVX on x86) require OS support for context switching. The cpu package already accounts for this.
Cache line padding - The architecture structs use CacheLinePad to avoid false sharing. This is already handled by the package.
Platform-specific availability - Feature flags are only meaningful on their respective architectures. On other platforms, all flags for that architecture will be false.
The cpu package supports feature detection on:
runtime - Go runtime provides some basic architecture informationgolang.org/x/sys/unix - Low-level Unix system callsgolang.org/x/sys/windows - Low-level Windows system calls