Explain why counterexamples violate specifications by analyzing formal specifications (temporal logic, invariants, pre/postconditions, code contracts), informal requirements (user stories, acceptance criteria), test specifications (assertions, property-based tests), and providing step-by-step traces showing state changes, comparing expected vs actual behavior, identifying root causes, and assessing violation impact. Use when debugging test failures, understanding model checker output, explaining runtime assertion violations, analyzing static analysis warnings, or teaching specification concepts. Produces structured markdown explanations with traces, comparisons, state diagrams, and cause chains. Triggers when users ask why something failed, explain a violation, understand a counterexample, debug a specification, or analyze why a test fails.
93
92%
Does it follow best practices?
Impact
96%
1.45xAverage score across 3 eval scenarios
Passed
No known issues
State machine violation trace and diagram
ASCII state diagram
0%
66%
Step-by-step trace
91%
91%
Status indicators in trace
0%
100%
Violation point identified
90%
100%
Expected vs actual table
90%
90%
Root cause identified
100%
100%
Buggy vs fixed code
40%
100%
Impact severity stated
0%
100%
Downstream effects listed
100%
100%
Specification clearly stated
100%
100%
One-sentence summary
100%
100%
Temporal logic violation with timeline and plain language
Plain language LTL translation
100%
100%
Operators explained
75%
100%
Timeline diagram present
100%
100%
Status markers in timeline
0%
50%
Violation point in timeline
70%
100%
Cause-effect chain
41%
100%
Root cause identified
100%
100%
Buggy vs fixed code
0%
100%
Impact severity stated
0%
100%
Real-world impact described
100%
100%
Non-technical audience addressed
100%
100%
Minimal counterexample and assertion chain for property-based test
All postconditions listed
100%
100%
Pass/fail indicators per postcondition
40%
100%
Failing postcondition detail
100%
100%
Minimal counterexample analysis
58%
100%
Bug class generalization
25%
100%
Root cause identified
100%
100%
Specific line referenced
100%
100%
Corrected code shown
100%
100%
Impact severity stated
0%
100%
Real-world consequences described
0%
100%
Actual values used throughout
100%
100%
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Table of Contents
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