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arm-cortex-expert

Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD).

60

1.19x

Quality

41%

Does it follow best practices?

Impact

93%

1.19x

Average score across 3 eval scenarios

SecuritybySnyk

Passed

No known issues

Optimize this skill with Tessl

npx tessl skill review --optimize ./skills/antigravity-arm-cortex-expert/SKILL.md
SKILL.md
Quality
Evals
Security

Evaluation results

100%

28%

High-Speed Audio ADC Capture on Teensy 4.x

DMA buffer alignment and cache coherency

Criteria
Without context
With context

32-byte buffer alignment

33%

100%

Buffer size multiple of 32

100%

100%

DTCM/non-cacheable placement

100%

100%

MMIO barrier: DMB before reads

0%

100%

MMIO barrier: DSB after writes

0%

100%

Cache maintenance or rationale

100%

100%

Complete driver structure

100%

100%

ISR and register annotations

100%

100%

Ping-pong / double-buffer logic

100%

100%

Tradeoffs documented

100%

100%

LPSPI/ADC platform limits

100%

100%

Without context: $0.6112 · 4m 13s · 12 turns · 13 in / 14,095 out tokens

With context: $1.0570 · 4m 54s · 37 turns · 62 in / 16,119 out tokens

100%

2%

Rust Sensor Monitoring Firmware for nRF52840

Rust interrupt-safe shared state

Criteria
Without context
With context

No static mut

100%

100%

Mutex<RefCell<Option<T>>> pattern

100%

100%

critical_section::with access

100%

100%

AtomicBool for flags

100%

100%

Acquire/Release ordering

100%

100%

SAADC calibration on init

100%

100%

Complete driver structure

80%

100%

Short critical sections

100%

100%

Concurrency rationale

100%

100%

GPIOTE channel usage

100%

100%

Without context: $0.9381 · 5m 19s · 22 turns · 22 in / 18,879 out tokens

With context: $1.1056 · 5m 33s · 31 turns · 517 in / 19,443 out tokens

80%

14%

STM32F4 Multi-Peripheral Data Logger Firmware

NVIC priorities and W1C register patterns

Criteria
Without context
With context

DMA/SPI at priority 0-2

0%

0%

UART at priority 3-7

0%

100%

Priority config comments

100%

100%

W1C status register clear

83%

100%

BASEPRI for critical sections

0%

0%

Short critical sections

100%

100%

Hardfault reads HFSR and CFSR

100%

100%

Hardfault captures stack frame

100%

100%

MMFAR/BFAR checked

75%

100%

Complete driver structure

100%

100%

Tradeoffs documented

100%

100%

Without context: $2.2122 · 13m 19s · 25 turns · 74 in / 49,090 out tokens

With context: $1.7383 · 8m 44s · 32 turns · 30 in / 33,118 out tokens

Repository
boisenoise/skills-collections
Evaluated
Agent
Claude Code
Model
Claude Sonnet 4.6

Table of Contents

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