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rtl-equivalence-checker

Hardware verification tool for checking functional equivalence between two RTL designs (Verilog). Use when users need to: (1) Verify if two RTL versions are functionally equivalent, (2) Compare original vs. refactored RTL code, (3) Validate design changes or optimizations, (4) Identify semantic vs. cosmetic differences, (5) Generate counterexamples for non-equivalent designs. Analyzes interface alignment, state variables, logic differences, and produces detailed equivalence verdicts with plain language explanations. Particularly effective for design verification, code reviews, and regression testing of RTL modifications.

Quality

87%

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SKILL.md
Quality
Evals
Security

Quality

Content

75%Weight 40%Scale 1-5

Reviews the quality of instructions and guidance provided to agents. Good implementation is clear, handles edge cases, and produces reliable results.

Highly actionable content with executable commands, real bundle files, and clearly sequenced workflows. The main weakness is redundancy: Overview, Tips, Limitations, and inline output examples repeat or over-expand material that could be consolidated or moved to the reference files.

Suggestions

Consolidate redundant sections: 'Overview' restates the frontmatter description, and 'Tips'/'Common Issues' largely restate guidance from 'Interpreting Results' and 'Advanced Options' — trimming these would directly improve conciseness, the lowest-scoring dimension.

Move the two full output-format example blocks to a reference file (e.g., references/output_examples.md) or shorten them to the verdict and explanation lines, keeping the body as an overview.

Reduce the 'Difference Types' section to a one-line cosmetic-vs-semantic summary and point to references/equivalence_patterns.md, which already contains the detailed examples.

DimensionReasoningScore

Conciseness

Mostly efficient — commands and analysis steps are tight and domain-specific — but several sections could be trimmed: 'Overview' restates the description, 'Tips' and 'Common Issues' repeat earlier guidance, and 'Limitations'/'Integration with Formal Tools' overlap ('Best for' vs. pre-analysis workflow). It avoids a 2 because nothing teaches concepts Claude already knows; the padding is redundancy rather than over-explanation.

3 / 5

Actionability

Fully executable, copy-paste-ready commands throughout ('python3 scripts/check_equivalence.py design_a.v design_b.v' with --clock, --reset, --reset-active, -o, --ignore-names, --max-depth), all of which exist in the bundle, plus per-use-case example commands and concrete sample outputs. This matches the 5 anchor: specific examples cover the common cases.

5 / 5

Workflow Clarity

Clear sequences exist (4-step Workflow, 5-step Analysis Process, numbered per-use-case approaches, verdict-driven actions in 'Interpreting Results') with error-recovery guidance ('No counterexample: increase max-depth'; 'False positive: use formal tools'). It misses 5 because validation checkpoints are implicit rather than explicit steps in the workflow; the destructive/batch cap does not apply since this is a read-only analysis tool.

4 / 5

Progressive Disclosure

Good structure: both references (equivalence_patterns.md, formal_tools.md) are real, well-signaled ('**See:** [equivalence_patterns.md](references/equivalence_patterns.md)'), one level deep, and indexed in References/Scripts sections. It misses 5 because the 331-line body inlines content that could be split out — two full ~25-line output-format blocks and the detailed Difference Types taxonomy — a minor organization gap.

4 / 5

Total

16

/

20

Passed

Description

92%Weight 40%Scale 1-5

Based on the skill's description, can an agent find and select it at the right time? Clear, specific descriptions lead to better discovery.

A strong description: concrete, comprehensive, third-person, with an explicit numbered 'Use when' trigger clause covering five realistic scenarios. The only gap is a few missing natural synonyms and file extensions (e.g., 'LEC', '.v').

DimensionReasoningScore

Specificity

The description lists multiple concrete actions — 'checking functional equivalence between two RTL designs (Verilog)', 'Compare original vs. refactored RTL code', 'Identify semantic vs. cosmetic differences', 'Generate counterexamples', 'Analyzes interface alignment, state variables, logic differences' — with comprehensive coverage in third-person voice. It exceeds the 4 anchor ('minor gaps in coverage') because both capability actions and analysis details are fully enumerated.

5 / 5

Completeness

Both 'what' ('checking functional equivalence... Analyzes interface alignment... produces detailed equivalence verdicts') and 'when' (explicit numbered 'Use when users need to: (1)...(5)' clause) are clearly and explicitly stated with concrete triggers. This matches the 5 anchor exactly rather than 4, where the 'when' would only be implicit or less specific.

5 / 5

Trigger Term Quality

Good natural-term coverage: 'functionally equivalent', 'RTL', 'Verilog', 'refactored', 'counterexamples', 'code reviews', 'regression testing'. It falls short of the 5 anchor because common synonyms and file extensions users would say — 'logic equivalence check (LEC)', '.v'/'.sv' — are absent, but it is well above the 3 anchor since most relevant keywords and variations are present.

4 / 5

Distinctiveness Conflict Risk

Clear niche — RTL/Verilog functional equivalence checking — with distinct triggers ('equivalence', 'counterexample', 'Verilog', 'refactored RTL') and minimal conflict risk; the broadest phrase ('code reviews') is qualified by 'of RTL modifications'. Not 4, since no closely related skill's territory is genuinely overlapped.

5 / 5

Total

19

/

20

Passed

Validation

100%

Checks the skill against the spec for correct structure and formatting. All validation checks must pass before discovery and implementation can be scored.

Validation — 16 / 16 Passed

Validation for skill structure

No warnings or errors.

Repository

ArabelaTso/Skills-4-SE

Path

skills/rtl-equivalence-checker/SKILL.md

Reviewed

Table of Contents

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